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Description: 自己总结的Altera_LVDS的IP核的设计及仿真分析,已在实际工程中应用到,并且带有源代码和仿真代码,总结的文档,非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
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Size: 3191808 |
Author: 何河
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Description: XILINX 官方的LVDS IP核,亲测可用。。。。。(XILINX official LVDS IP kernel, pro test available.....)
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Size: 282624 |
Author: shanyuan001
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Description: 基于verilog IP核的FFT工程,512位FFT运算,(FFT engineering based on Verilog IP kernel and 512 bit FFT operation,)
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Size: 54045696 |
Author: paulwww
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Description: verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
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Size: 16939008 |
Author: 嘿哟
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Description: verilog基于DDR3 xilinx IP核 的DDR3的读写控制,方便学习(it is based on DDR3 IP core of xilinx)
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Size: 1024 |
Author: superali
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Description: GTP IP核,高速通信必须学习的部分。(GTP IP kernel, part of high-speed communication that must be learned.)
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Size: 21694464 |
Author: tian682018
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Description: AD9361 IP 核,Linux版本,Vivado2014.2(AD9361 IP core, used on Linux, Vivado2014.2.)
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Size: 797696 |
Author: 小陈3
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Description: AD9361 IP核,Windows版本,Vivado2014.2(AD9361 IP core, used on Windows, Vivado2014.2)
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Size: 1341440 |
Author: 小陈3
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Description: AD9361 IP核,Linux版本,Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
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Size: 772096 |
Author: 小陈3
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Description: AD9361 IP核,Windows版本,Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
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Size: 1393664 |
Author: 小陈3
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Description: AD9361 IP核,Linux版本,Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
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Size: 932864 |
Author: 小陈3
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Description: AD9361 IP核,Windows版本,Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
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Size: 1743872 |
Author: 小陈3
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Description: verilog编写的spram,包含顶层模块,控制模块和spram本体,其中spram为Altera提供的ip核,已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
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Size: 2857984 |
Author: keykai
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Description: IP core fft verilog code example
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Size: 5766144 |
Author: mrv
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Description: 锁相环IP核的使用,包括详细的配置,适合学习使用;(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
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Size: 232448 |
Author: 声声不洗
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Description: rom ip核的配置,以及测试文件,适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
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Size: 4237312 |
Author: 声声不洗
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Description: ISE工程,并行nor flash的读、写、擦出,其中有个调用FIFO16-16的IP核,已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
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Size: 1124352 |
Author: 张超
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Description: 如题,各种veirlog 基础代码大全,虽功能不及ip核,但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
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Size: 32768 |
Author: halibote
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Description: 基于S10新品的2x2矩阵乘模块,附带双精度的乘法,除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
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Size: 590848 |
Author: Rdddd |
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Description: 使用verilog语言实现了udp发送 接收(Implementation of UDP sending and receiving)
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Size: 9023488 |
Author: zhao1234 |
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